Anora

DFT architecture, implementation, verification, pattern generation
Post silicon test bring-up, fault diagnosis, yield ramp

Tools and Technology

Cadence
Mentor Graphics
Synopsys
Logic – Scan and BIST
Fault models
Memory BIST
High speed DFT
Analog DFT
Diagnosis - yield ramp
Test bring-up
Test stability and performance
System test support

DFT – RTL level

DFT architecture
DFT specification
DFT RTL development
DFT RTL verification
Scan insertion
Coverage analysis

DFT – Gate level

DFT timing constraints
Gate level simulations
Test power and IR analysis

Test Pattern Handoff

Fault models
- Stuck-at
- Transition
- Path delay
- Iddq
- Cell-aware
- Small delay
Memory BIST
Mixed-signal tests
Embedded IP

Post Silicon Support

Test Bring-up
Root cause failures
Desktop testers
Defect diagnosis with scan
Analyze test escapes